The Reed-Solomon Code (hereinafter, RS code) is mainly used for recording media and external coding of digital transmissions, from the appropriateness in relation to the quality of the encoding efficiency and the error burst.
For example, the error correction code that is used with a compact disc is called the CIRC correction code (cross interleaved Reed-Solomon code); this is a product code that is combined with the interleave method. RS (28, 24) code is used as the external code, and RS (32, 28) code as the internal code; these are called the C2 code and the C1 code, respectively. In either code, the RS encoding symbol is constructed of 1 byte, and a single RS decoding block contains a parity check string of 4 bytes.
Generally, the RS code is a check string of 2t symbols, and correction of the t symbol is possible. In the correction of the t symbol, it is necessary to know the t units of error positions, and the value of t units of error corresponding to the respective errors. The RS coding obtains an independent linear formula for 2t units by performing a syndrome calculation at the decoding side in relation to the generation of t units of error. By solving this formula, the error position for the above-mentioned t units, which is an unknown number of 2t units, and the value of the error of the above-mentioned t units corresponding to the respective error positions, can be found.
On the other hand, as for adopting a construction of a product code like the CIRC code, by applying a erasure flag to the RS-coded block for which correction could not be done at the internal RS decoding in relation to the internal code and the RS-encoded block in which the possibility of error correction is comparatively high, a erasure error correction becomes possible in the external RS decoding corresponding to the external code. The erasure symbols for the internal code to which the erasure flags were applied are dispersed in multiple external RS-encoded blocks by means of de-interleaving. In the erasure error correction, by assuming that there is an error present in the above-mentioned erasure symbol, the simultaneous formulas that are obtained from the syndrome calculations are solved. Since the solved error positions are already known, the value of the error for the maximum 2t can be solved. In other words, it is possible to error-correct a maximum of 2t symbols by executing the erasure error correction for the RS codes having check strings for 2t symbols.
The method for the erasure error correction is explained by offering an example of the CIRC code.
In the case of the CIRC code, by applying a erasure flag in the RS decoding (C1 decoding) for the C1 code, which is the internal code, the erasure error correction is possible in the RS decoding (C2 decoding) for the C2 code, which is the external code. Because t=2 in both the C1 code and the C2 code, in C1decoding, correction of a maximum 2 bytes is possible, but in the erasure error correction of the C2 decoding, the correction of a maximum of 4 bytes is possible. The syndrome s.sub.0 to s.sub.3 and the error value e.sub.1 to e.sub.4 in the C2 code can be found as follows.
The code-generating polynomial expression Ge (x) for the CIRC code is shown by Formula 1 below.
[Mathematical formula 1] ##EQU1##
Here, .alpha. is the primitive element for the Galois field. At this time, s.sub.0 to s.sub.3 obtained by means of the syndrome calculations from the input string have the relationship shown by the following Formula 2 between the above-mentioned x.sub.1 to x.sub.4, and e.sub.1 to e.sub.4.
[Mathematical formula 2] ##EQU2##
Here, the symbol ".multidot." indicates multiplication over the Galois field, and the symbol "+" indicates addition over the Galois field. Below, as for the four basic mathematical operations between the elements of a given Galois field, the calculations on that Galois field are shown.
If the error values e.sub.1 to e.sub.4, which are unknown numbers, are found by solving the simultaneous formulas, the above-mentioned Formula 2 becomes as follows.
First, e.sub.4 is obtained as the below listed Formula 3.
[Mathematical formula 3] ##EQU3##
One of the simultaneous equations is reconstructed by substituting the e.sub.4 that was obtained in the above-mentioned Formula 2. In other words, as for the Galois field that was used in the CIRC code, by correcting it as in Formula 4 below, noting the fact that the addition and the subtraction are the same, the simultaneous Formula of the above-mentioned Formula 2 is transformed to Formula 5 below.
[Mathematical formula 4] EQU s0.rarw.s0+e4 EQU s1.rarw.s1+x4.multidot.e4 EQU s2.rarw.s2+x4.sup.2 .multidot.e4 (4)
[Mathematical formula 5] ##EQU4##
As for this, the solving of the simultaneous equations is a method that is frequently used when finding the sequence in manual calculations. If e.sub.3 is found by solving the simultaneous equation of Formula 5, it becomes like the below listed Formula 6.
[Mathematical formula 6] ##EQU5##
By executing the corrections in the same manner, the simultaneous formula of the above-mentioned Formula 5 is modified as in Formulas 7 and 8 below.
[Mathematical formula 7] EQU s0.rarw.s0+e3 EQU s1.rarw.s1+x3.multidot.e3 (7)
[Mathematical formula 8] ##EQU6##
Also, if e.sub.2 is found by solving the simultaneous equation of Formula 8, it becomes Formula 9 below.
[Mathematical formula 9] ##EQU7##
Next, Formula 10 below is obtained by substituting the e.sub.2 that was found in the above-mentioned Formula 8.
[Mathematical formula 10] EQU e1.rarw.s0+e2 (10)
In this manner, the error values e.sub.1 to e.sub.4 can be found sequentially.
In the above-mentioned method, in order to distinguish between those which were originally held as information and the calculation operations that were performed at the time of the actual decoding, the symbols "=" and ".rarw." are used in different ways. In other words, the Formulas corresponding to the actual decoding calculations are Formulas 3, 4, 6, 7, 9, and 10, and in the Galois field, at least 23 additions, 17 multiplications, and 3 divisions are necessary.
On the other hand, in the event the erasure error correction is not performed, corrections (double error corrections) can be performed for a maximum of 2 bytes in the C2 decoding. At this time, the error values e.sub.1, e.sub.2, and the error positions X'.sub.1, X'.sub.2 are found from the syndromes s.sub.0 to s.sub.3.
Above, the quadruple erasure error correction, in other words the number of erasure positions, is the decoding calculation process for 4 cases.
Below, an explanation is given in regard to the Reed-Solomon decoding device used in the past.
FIG. 10 is a construction diagram of the Reed-Solomon decoding device used in the past.
As is shown in FIG. 10, the Reed-Solomon decoding device 1 is provided with the memory block 2, the bus I/F block 3, and the decoding calculation processing section 4.
The memory block 2 is provided with the cache memories 5, 6, and the switches 7, 8.
The switch 7 selectively outputs the input data to the cache memories 5, 6. The switch 8 selectively outputs the stored content of the cache memory 5 to the correction operation implementer 12.
The bus I/F block 3 is provided with the input parameter calculator 9, the register B.sub.OUT 10, the binary counter 11, the correction operations implementer 12, and the register B.sub.IN 13.
The decoding calculation processing section 4 is provided with the switch 14, the register G.sub.IN 15, the register G.sub.OUT 16, and the decoding calculator 17.
FIG. 11 shows the chronology of the data and the construction elements during the operation of the Reed-Solomon decoding device 1, (A) shows the input data, (B) the output data, (C) the storage condition of the register B.sub.OUT 10, (D) the storage condition of the register B.sub.IN 13, (E) the storage condition of the register G.sub.OUT 16, (F) the storage condition of the register G.sub.IN 15, and (G) the processing condition of the decoding calculator 17, respectively.
As is shown in FIG. 11, when the input/output is performed for the input data related to the C1 code at the cache memory 5 of the memory block 2, as for the bus I/F block 3, the calculations are performed for the decoding calculation input parameters at the input parameter calculator 9 for the input data related to the C1 code, and the correction operations are performed by the corrections operation implementer 12. Also, at this time, at the decoding calculations processing section 4, the C2 code processing is performed in regard to the input data related to the C2 code.
Also, when the input/output is performed for the input data related to the C2 code in the cache memory 6, as for the bus I/F block 3, the calculations are performed for the decoding calculations input parameters by the input parameter calculator 9 for the input data related to the C2 code, and the correction operations are performed by the correction operation implementer 12. Also, at this time, at the decoding calculations processing section 4, the C1 decoding process is performed in regard to the input data related to the C1 code.
Here, that which is referred to as the decoding calculation input parameters, basically, is the syndrome (S) and the erasure position (I).
The syndrome (S) is calculated by means of combining the input parameter calculator 9 and the register B.sub.OUT 10 shown in FIG. 10.
FIG. 12 is a construction diagram of the input parameter calculator 9 and the register B.sub.OUT 10.
As is shown in FIG. 12, the input parameter calculator 9 is provided with the multipliers 24 to 27, the adders 20 to 23, the error flag detector 28, and the distributor 29.
Also, the register B.sub.OUT 10 is provided with the registers (30 to 33) and the registers 34 to 37
As for the multipliers 24 to 27, the multiplier coefficients are the multipliers for a Galois field of fixed values, and perform the multiplications of x.alpha..sup.0, x.alpha..sup.1, x.alpha..sup.2, x.alpha..sup.3, respectively.
The error flag detector 28 detects whether or not the error flag contained in the input data is a "1."
The distributor 29 outputs and stores the output of the binary counter 11 which operates corresponding to each RS symbol position contained in the input data in any of the registers 34 to 37 of the register B.sub.OUT 10.
The storage results of these registers 34 to 37 indicate the erasure positions (I).
The erasure positions (I) are converted to the expression of the Galois field, in other words, from .sup.i to .alpha..sup.i by means of a later presented converter, by the decoding calculator 17 shown in FIG. 10.
Specifically, I={i.sub.1, i.sub.2, i.sub.3, i.sub.4 } is converted to X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 }.
The decoding calculations corresponding to the above-mentioned Formulas 3, 4, 6, 7, and 10 in the case of executing the quadruple erasure error corrections are performed by the decoding calculation processing section 4, and using the decoding calculation input parameters S={s.sub.0, s.sub.1, s.sub.2, s.sub.3 } from the register B.sub.OUT 10, and the X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 } that was obtained by converting the I={i.sub.1, i.sub.2, i.sub.3, i.sub.4 }, the decoding calculation output parameters E={e.sub.1, e.sub.2, e.sub.3, e.sub.4 } and X'=X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 } are obtained. In the event the erasure error correction is not performed, in the above-mentioned double error correction, by using the decoding calculation input parameters S={s.sub.0, s.sub.1, s.sub.2, s.sub.3 }, the decoding calculation output parameters E={e.sub.1, e.sub.2 } and X'={x'.sub.1, x'.sub.2 } are obtained.
The error positions X for X' are converted to index numbers, in other words, from .alpha..sup.i to i in the later explained converter by the decoding calculation processing section 4. Specifically, X'=X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 } is converted to I={i.sub.1, i.sub.2, i.sub.3, i.sub.4 }, and X'={x'.sub.1, x'.sub.2 } is converted to I'={i'.sub.1, i'.sub.2 }.
FIG. 13 is a construction diagram of the correction operation implementer 12 and the register B.sub.IN 13.
As is shown in FIG. 13, the correction operation implementer 12 is provided with the comparator 40, the adder 45, and the logic gate 46.
Also, the register B.sub.IN 13 is provided with the registers 41 to 44 and the registers 47 to 50.
The bus I/F block 3 executes the correction operations by using the error value (E) and the error positions (I') that are input from the register G.sub.OUT 16.
The binary counter 11 operates according to the switching of the output from the switch pad memories 5, 6 by means of the switches 7, 8, and when the binary count value of the binary counter 11 matches any one of the (i'.sub.n) construction elements for the error position (I'), a corresponding error value en is output to the adder 45 from the logic gate 46. Also, at the adder 45, the Galois field calculations are performed in regard to the error value e.sub.n and the data output of the memory block from the switch 8, and the addition results become the output data.
Next, an explanation is given in regard to the decoding calculation processing section 4.
FIG. 14 is a construction diagram of the decoding calculation processing section 4.
As is shown in FIG. 14, the decoding calculation processing section 4 is provided with the microcode ROM 50, the register 51, the destination controller 52, the working register 53, the GLU (Global Logic Unit) 54, and the port selector 55.
As in the CIRC code, t is smaller than 4, and in the event the solution is found directly from the simultaneous formula, and when the processing speed is comparatively slow, a RISC (Reduced Instruction Set Computer) type of device can be used as the decoding calculation processing section 4.
In the decoding calculation processing section 4, each calculation is sequentially performed, and the calculation sets are shared at GLU 54. Also, a series of calculation processes are microcoded, are stored in the microcode ROM 50 as instruction codes, and the process routine (routine for readout from the memory) is controlled by means of the ROM address from the sequencer 51.
Also, during the operation, the calculation results are temporarily stored in the multiple working registers 53 that were initialized beforehand, but as to which working register 53 to store in, this is recorded in the destination control code within the instruction code.
According to this method, the process speed is limited, but along with being able to downsize the device due to sharing of the GLU 54, the freedom of design can be increased due to the microcoding of the calculation processes.
For example, the addition of two elements of the Galois field is equivalent to each bit of an exclusive OR logic operation, and can be realized in one step by the decoding calculations processing section 4. In other words, the GLU 54 includes the function of an exclusive OR logic operation for each bit. However, the multiplication of a Galois field is far more complicated compared to addition, and if an attempt is made to realize this by using ROM, one byte of output is obtained for an address input of two bytes, and the scale becomes extremely large.
An explanation is given in regard to the construction of the GLU 54.
FIG. 15 is a construction diagram of the GLU 54.
As is shown in FIG. 15, the GLU 54 is provided with the operation logic 60, 61, the converters 62, 63, and the operation selector 64.
In the GLU 54, the respective elements of the Galois field for the two input data a, b are converted to the values for the indices for the corresponding original elements, in other words, .alpha..sup.i is converted to i by the converter 62, and additions between the same indices are executed. Then, these addition results that have been obtained are converted to the element for the corresponding Galois field by the converter 63, in other words, i is converted to .alpha..sup.i.
For example, the multiplication of .alpha..sup.v and .alpha..sup.w is executed, and in obtaining .alpha..sup.v+w, the four calculations shown in the following Formula 11 are necessary, and at least four steps are required at the GLU 54.
[Mathematical formula 11] ##EQU8##
Division is also performed in the same manner, and subtraction is executed in place of the addition in the multiplication.
Therefore, in the above-mentioned method, in determining the error values e.sub.1 to e.sub.4, since the multiplication-division in the above-mentioned Formulas 3, 4, 6, 7, 9, and 10 are done 20 times, even with just this, 80 steps or more become necessary. If the 23 steps of addition are included in this, it becomes a total of more than 103 steps. Because of this, it cannot respond to the requirement of high-speed processing.
In the event t is greater than 4, because the solving of one of the simultaneous equations such as is shown in the above-mentioned Formula 2 is unrealizable, a repeating algorithm such as a Euclidean decoding method is used.
However, in either case, 4 steps are also required in the multiplication and division of the Galois field, and the realization of high-speed processing is difficult.
On the other hand, the requirement for speed in the data reproduction of a CD-ROM at the present time has increased from 2.times. speed to 12.times. speed, and the limits for the number of processing steps for error correction is becoming increasingly restricted every da. Furthermore, this means that the reading errors of the optical system are also naturally increasing, and it is desired for the reinforcement of the correction performance by means of the above-mentioned erasure error correction to be strengthened. In other words, it is necessary to realize a higher function with a fewer number of steps.
In realizing C1 decoding and C2 decoding corresponding to 12.times. speed, for example, if 1 step of the calculations is completed within 1 clock cycle of 16 MHz, it is necessary for the decoding of both C1 and C2 to be executed in 192 steps. Since this condition includes the peripheral processing such as branch processing, it is required for the processing of the core of the C2 decoding to be realized within 1/4 of that.
However, in the construction used in the past, for example, when the erasure error correction was performed with C2 decoding, a number of calculations steps of more than 103 were required just in the processing for that correction core, and it could not respond to the requirements of high-speed processing.
Also, in the above-mentioned Reed-Solomon decoding device 1, as is shown in FIG. 10, along with the two registers B.sub.OUT 10 and B.sub.IN 13 provided in the bus I/F block 3, the two registers G.sub.OUT 16 and G.sub.IN 15 are provided in the decoding calculation processing section 4. Also, in the Reed-Solomon decoding device 1, because calculations using the erasure position and the error position are performed by the index expression of the Galois field, as is shown in FIG. 15, in the GLU 54 of the decoding calculation processing section 4, the converter 62 that converts the element of the Galois field to the index for the corresponding original space, and the converter 63 that performs its reverse conversion, become necessary.
Because of this, with the Reed-Solomon decoding device 1, there is the problem that it becomes a large-scale device.
This invention was made reviewing the prior technology, and the purpose of this invention is to offer a Reed-Solomon decoding device that accomplishes a downscaling of the circuit.
Also, the purpose of this invention is to offer a Reed-Solomon decoding device in which high-speed processing is possible.